Investigation on Fin and Gate Line Edge Roughness Effects for Sub-22 nm Inversion-Mode and Junctionless FinFETs
نویسنده
چکیده
In this paper we investigated the line edge roughness (LER) effects on the 22-nm and 14nm inversion mode (IM) and jounctionless (JL) FinFETs by TCAD simulation. We examined the gate LER (GLER) effects and the fin LER (FLER) effects on the device variability separately. The simulation results show that the GLER-induced device variations will increase as the channel length decrease as expectation; however, the FLERinduced device variations will decrease as the channel length decrease. Consequently, in the deep nanometer regime, GLER-induced device variations will be a major problem for FinFETs as far as LER effects are concerned. Besides, LER will cause larger variation on the threshold voltage of the JL FinFET than that of the IM FinFET.
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